Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA

Cárdenas López, Daniel Felipe

2010-11

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This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques implemented on a logical core (FPGA) in order to extract the instantaneous phase error information and an external VCO for generating the exact sampling clock that drives the ADC at the receiver.

DSP; INTERFACES (COMPUTADORES);